One example of semiconductor storage devices is a non-volatile memory, which is an element in which information stored therein remains even if power is turned off. And, by mounting such a non-volatile memory cell and a logical semiconductor device together on the same silicon substrate, a high-performance semiconductor device can be achieved. Such a high-performance semiconductor device is widely used as an embedded-type microcomputer in industrial machines, household electrical appliances, automobile-mounted devices and the like.
One example of cell structures of such non-volatile memories is a split-gate-type memory cell formed of a MOS transistor for selection (a select transistor or a memory-cell select transistor) and a MOS transistor for storage (a memory transistor) (for example, refer to Japanese Patent Application Laid-Open Publication No. 5-48113 (Patent Document 1), Japanese Patent Application Laid-Open Publication No. 5-121700 (Patent Document 2), “IEEE Symposium on VLSI Technology”, U.S.A., 1994, pp. 71-72 (Non-Patent Document 1), and “IEEE Symposium on VLSI Technology”, U.S.A., 1997, pp. 63-64 (Non-Patent Document 2)). In this structure, a source side injection (SSI) scheme with high injection efficiency can be used. Therefore, features of this structure include increase in writing speed, reduction in an area of a power supply unit, and also reduction in an area of peripheral circuits because the memory-cell select transistor and a transistor connected thereto can be composed of low-voltage system transistors with small element area.
Charge-holding schemes in a MOS transistor for storage include a floating-gate scheme in which charges are stored in electrically-isolated conductive polycrystalline silicon (for example, refer to Patent Document 2 and Non-Patent Document 1) and a MONOS scheme in which charges are stored in a dielectric film having a property of storing charges, such as a silicon nitride film (for example, refer to Patent Document 1 and Non-Patent Document 2). To get memory chips and memory modules to operate at high speed by using any of these memory-cell structures, it is effective to increase a so-called “cell current” in reading of the memory cell.
For the select transistor, a normal MOS transistor using silicon oxide (SiO2) or silicon oxynitride (SiN) as a gate dielectric film can be used. In this case, according to a process dimension, by using a known technology such as optimization of an impurity density profile of a channel, it is possible to manufacture a high-performance select transistor, with suppressing a leak current in an OFF state. And, as for a memory transistor, by decreasing a threshold voltage determined by a polarity and amount of held charges and the impurity density profile of the channel, a larger “cell current” can be achieved with respect to the same voltage of a memory gate (a gate of the memory transistor).
In the MONOS scheme, the following technology has been known as a technology for decreasing the threshold voltage.
In the case of an n-type memory transistor in which conductive carriers of a channel are electrons, by applying a positive potential to a diffusion layer on a memory-gate side (source region or drain region), a strong inversion can be generated in a region where a memory gate at an end of the diffusion layer and the diffusion layer overlap each other. With this, a band-to-band tunneling occurs, therefore, holes can be generated (for example, refer to “1987 IEEE International Electron Devices meeting, TECHNICAL DIGEST”, U.S.A., 1987, pp. 718-721 (Non-Patent Document 3)). In this memory cell, the generated holes are accelerated in a channel direction and drawn by a bias of the memory gate to be implanted into a silicon nitride (SiN) film, therefore, a state of the memory transistor with a low threshold voltage (erase state) can be realized.
Also, Japanese Patent Application Laid-Open Publication No. 2004-186452 (Patent Document 3) discloses a technology in which a channel region of a MONOS memory transistor is doped with counter impurities to decrease a threshold voltage of the memory transistor. At this time, a channel below the memory transistor includes both of an acceptor-type impurity doped into a channel region of a select transistor and a donor-type impurity which is a counter impurity doped into a channel under the memory transistor only. And, the acceptor-type impurity doped into the channel region of the select transistor is adjusted so that an OFF leak is small.
Furthermore, a technology about a flat-band voltage of a MISFET is described in “Symp. on VLSI technology”, U.S.A., 2003, p. 9, C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hedge, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R, Rai, L. Hebert, H. Tseng, B. White, and P. Tobin (Non-Patent Document 4).
Still further, a technology about variation in threshold voltage due to fluctuations of impurities is described in “IEEE Transactions on Electron Devices, ED-41”, U.S.A., 1994, p. 2216, T. Mizuno et al (Non-Patent Document 5).
And, a technology about Fermi level pinning is described in “IEEE Symposium on VLSI Technology”, U.S.A., 2004, p. 214 by L. Pantisano et al (Non-Patent Document 6).